1. Field of the Invention
The present invention relates to a liquid crystal display device and fabrication method thereof.
2. Discussion of the Related Art
In general, a liquid crystal display device (LCD) displays pictures corresponding to video signals on a liquid crystal panel having a plurality of liquid crystal (LC) cells arranged in a matrix configuration by adjusting light transmittance each of the LC cells.
Thin film transistors (TFTs) are used as a switching element for switching the LC cells. The TFTs generally use amorphous silicon or polycrystalline silicon (polysilicon) as a semiconductor layer. The amorphous silicon (a-Si) TFT has an advantage of relatively good uniformity, resulting in a more stable TFT. However, the a-Si also has a disadvantage that carrier mobility is low and thus response rate is slow. Hence, it is difficult to employ the a-Si TFT as a driving element, such as a gate driver or a data driver, for a high resolution display panel requiring a rapid response time.
A polysilicon TFT is suitable for a high resolution display panel requiring a rapid response time due to its high carrier mobility, and permits peripheral driving circuits to be built in the display panel. Accordingly, an LCD employing the polysilicon TFTs is preferred for high resolution.
FIG. 1 is a schematic plane view of an LCD employing polysilicon TFTs according to the related art. Referring to FIG. 1, the LCD includes an image display part 196 having a matrix of a plurality of pixels, a data driver 192 for driving data lines of the image display part 196, and a gate driver 192 for driving gate lines 102 of the image display part 196. The image display part 196 includes LC cells arranged in a matrix configuration so as to display an image.
Each of the LC cells is connected at a crossing point of the gate line 102 and the data line 104, and is driven by a TFT 130 employing n-type impurity-doped polysilicon as a switching element. The n-type TFT 130 applies a video signal from the data line 104, i.e., a pixel signal in response to a scan pulse from the gate line 102 and charges the LC cell according to the video signal. In response, the LC cell adjusts light transmittance according to the extent to which it is charged.
The gate driver 194 sequentially drives the gate lines 102 during a horizontal period every frame depending on a gate control signal. The TFTs 130 are sequentially turned on in horizontal rows by the gate driver 194 so that the appropriate video signal on the data line 104 is connected to the proper the LC cells.
The data driver 192 performs a sampling of a plurality of digital data signals every a horizontal period and converts the sampled digital data signal into an analog data signal. The data driver 192 supplies the analog data signal to the data lines 104.
Accordingly, the LC cells connected to the TFTs are turned on to adjust light transmittance in response to a data signal of each of the data lines 104.
The gate driver 194 and the data driver 192 include driving elements connected in a CMOS structure. The driving element is made in one large TFT having a large channel width (W1) such that a large amount of current flows for a relatively high switching voltage. The driving element is made of polysilicon for a rapid response time.
FIG. 2 is a plane view of a driving element of a driving circuit part in an LCD according to the related art, and FIG. 3 is a sectional view taken along the line I-I′ of FIG. 2.
Referring to FIGS. 2 and 3, the driving element having one TFT includes an impurity (n+ ions or p+ ions)-doped active layer 174, and a gate electrode 166 overlapping a channel region 174C of the active layer 174 with a gate insulating layer 142 between the gate electrode 166 and the channel region 174C. The driving element also includes source electrode 168 and drain electrode 170 insulated from the gate electrode 166 with interposing an interlayer insulating layer 156, and a passivation layer 148 formed on the source electrode 168 and the drain electrode 170. FIG. 3 further illustrates a substrate 120 and a buffer layer 116.
The source electrode 168 and the drain electrode 170 are respectively connected, through source contact hole 184S and drain contact hole 184D, to the source region 174S and drain region 174D, which are implanted with impurities. Source and drain contact holes 184S and 184D provide contact through gate insulating layer 142 and the interlayer insulating layer 156. The passivation layer 148 is formed on the source electrode 168 and the drain electrode 170 to protect the driving element.
The driving element having one TFT has an advantage in that a large amount of current flows through the device and has a disadvantage in that a large amount of heat, is generated due to the large amount of current. Hence, to radiate heat generated in the channel 174C, the related art provides a driving element having a multi channel structure where TFTs having a plurality of small channel widths W2 are connected in parallel.
The driving element of the driving circuit part of the LCD illustrated in FIG. 4 is designed such that a sum of respective channel widths W2 is basically equal to one channel width W1 and a plurality of unit TFTs having a unit channel 277 have active layers separated from one another and connected in parallel.
In the plurality of unit TFTs having active layers separated from one another, the source and drain contact holes 284S and 284D are disposed at adjacent TFTs. FIG. 5 illustrates a section structure taken along the line II-II′ of FIG. 4. FIG. 5 illustrates a section taken along the line II-II′ on a drain electrode of FIG. 4, which is basically the same in structure as the source contact holes of the unit TFTs.
As illustrated in FIGS. 4 and 5, the plurality of TFTs are formed on a lower substrate 220 such that an interval between the respective unit channels 277 is constant within a limited distance, thereby forming multiple channels. Source and drain electrodes 268 and 270 are respectively in contact with the active layer 274 through the source and drain contact holes 284S and 284D. A passivation layer 248 is formed on the source and drain electrodes 268 and 270.
In the TFT having the multi channels divided at an equal interval, heat buildup, as it occurs in the center of a single channel, is reduced. Specifically, heat generated from the channel 277 of the TFT is absorbed by a gate insulating layer 242 and an interlayer insulating layer 256. The gate insulating layer 242, the interlayer insulating layer 256, and a buffer layer 216 are made of insulator such as SiO2 having a low dielectric and a low thermal conductivity, which thereby decreases parasitic capacitance.
Heat is generally not sufficiently dissipated from the gate insulating layer 242 and the interlayer insulating layer 256 between the drain contact holes 284D. The excess heat degenerates the devices and disturbs smooth current flow and performance of the driving element. This deterioration may cause abnormal operation and failure of the driving element.